Dialogic DSI SPCI Network Interface Boards Spécifications télécharger pdf (Page 103)

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DSI SS7HD Network Interface Boards Programmer's Manual Issue 11

103

4.5.3 MVD_MSG_CLK_IND - Clock Event Indication

Synopsis

Message issued by the board to indicate on-board clocking related events.

Format

MESSAGE HEADER

Field Name

Meaning

type

MVD_MSG_CLK_IND (0x0e23)

src

MVD_TASK_ID

dst

MGMT_TASK_ID

rsp_req

hclass

status

event_id

err_info

len

The MVD_MSG_CLK_IND message header uses the following parameter:

event_id

Specifies the event that caused the indication to be generated. The following table

shows the possible values and their meanings.

Value

Description

Phased Locked Loop (PLL) entered holdover mode

Issued by boards acting as primary or secondary clock master when its nominated clock

reference becomes unavailable. The phase-locked-loop starts operating in holdover mode,

continuing to generate an on-board clock at the same frequency as the last valid reference

signal.

PLL left holdover mode

The nominated clock reference for a primary or secondary master board has become

available and is now being used as the input to the board’s clock circuitry.

CT Bus clock set A fail

The CT Bus clock set A signals are not being correctly driven.

CT Bus clock set A recover

The CT Bus clock set A signals are being driven.

CT Bus clock set B fail

The CT Bus clock set B signals are not being correctly driven,

CT Bus clock set B recover

The CT Bus clock set B signals are being driven.

Master clock changeover

The board issuing this indication has automatically changed from secondary master to

primary master role for the clock set it was configured to drive.

1 2 ... 98 99 100 101 102 103 104 105 106 107 108 ... 124 125

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